In source synchronous signaling, a data strobe clock is driven by the transmitting device along with the data. The clock and data paths from transmitter to receiver are matched. At the receiving device the data strobe clock is used to latch incoming data. In Double Data Rate (DDR) SDRAM memory systems, the external databuses are bidirectional. Write data is sent to the memory from a memory controller and read data is sent from the memory to the controller. When no data is being sent, the bus returns to a tri-state level defined by the bus transmission line termination voltage.
Control of the bidirectional data strobe clock also changes depending on which device is driving data onto the databus. The data strobe clock input on the controller and the memory device must be gated by an enable signal to prevent the spurious clock edges created by a tri-stated clock input level from triggering internal data capture. When neither the memory controller nor the memory is driving the data strobe, the data strobe line will be pulled to the bus termination voltage by the termination resistor. For DDR and DDR2 memories, the termination voltage Vterm is Vddq/2, which is the same as the input buffer reference voltage Vref. As a result, the data strobe input buffer produces an indeterminate value, which may change between ‘0’ and ‘1’ depending on noise. On the memory chip this is easily accomplished because the write data instruction and the write data itself arrive source synchronously from the controller and the skew between the two sets of signals will be less than one bit period. Before the first active edge of the data strobe clock DQS there is a 2 bit preamble period during which DQS is driven low. During this time the memory chip can assert the enable signal.
During read operations the alignment between read command and read data on the bidirectional bus is much less certain. The delay through the command and address output drivers, through the package and printed circuit board connections to the memory device, back through the read data output buffers, package, and printed circuit board, and finally through the input buffers of the memory controller can vary by many bit periods depending on the system configuration and operating conditions.
A first problem associated with this alignment of read command and data is to determine, on system initialization, where in time to position the read data DQS enable signal so that it falls within the 2 bit preamble. A second problem is how to adjust for timing drift during operation caused by temperature or supply voltage drift. A third problem is how to transfer data clocked in with DQS to the system clock domain when the phase between the DQS clock and master system clock CLK can be completely arbitrary.
These problems did not exist in single data rate SDRAMs because there was no DQS clock and read data had to meet setup and hold requirements with respect to the master system clock CLK which originates from the controller.
Quad Data Rate (QDR) SRAM does not have the problem because separate read and write data busses exist with their own dedicated clocks. Since the clocks do not have to be tri-stated there is never any indeterminate state.
An application of a bidrectional data strobe signal to DDR SDRAM is disclosed in U.S. Pat. No. 6,889,336 granted to A. M. Schoenfeld et al. on May 3, 2005. At the initial DDR operating speeds DDR267 and DDR333, the 2 bit preamble period was still relatively large, 7.5 ns and 6.66 ns respectively. It was still possible to accommodate a range of system designs and operating conditions with fixed timing on the internal DQS enable. With DDR400 and DDR2 devices ranging from DDR2-400 to DDR2-800, there is a need for dynamic adjustment of the DQS enable time. An example set of typical loop-around read timing delays of a chip-to-chip controller to DDR SDRAM are as follows:
Delay from;min.max.Command latch to controller pin1.0 ns3.0 nsPCB trace to DDR SDRAM0.5 ns1.5 nsSDRAM command in to data out−0.5 ns  0.5 nsPCB trace to controller0.5 ns1.5 nsController pin to data latch1.0 ns3.0 nsTOTAL2.5 ns9.5 ns
The read data timing can vary by more than the width of the DQS preamble interval at data rates for DDR400 and higher. Fixed timing is not a robust solution.
As an example, several implementations of DQS gating are described in the LSI Logic 0.11 um DDR2 PHY document cw000733—1—0 dated February 2005. The PHY actually supports three different approaches for enabling the DQS read strobe, using a signal called GATEON.
The first approach “Programmable GATEON” allows the user to program the timing of GATEON based on a programmable delay register and the time the read command is issued. Read data training is required with this scheme. Read data training involves attempting a number of read operations with different delay register settings, finding the settings for which expected data is properly received, and then setting the delay register somewhere in the middle of the pass range. A disadvantage of this approach is that it requires higher level intelligence somewhere in the controller, and a significant amount of time during system initialization to determine the optimum setting. Also, it cannot accommodate timing drift during operation.
The second approach is called “Feedback GATEON”. A signal is generated and sent to a pin in the same way a command is generated. This signal can be routed along a PCB trace with the same length and loading as the command signal to the memory and back to the controller. At the controller the delayed signal is used to trigger the DQS enable. The disadvantage of this approach is that it requires 2 additional pins, PCB traces, and consumes power. It does not perfectly match the actual command to read data loop-around delay.
The final approach is called “External GATEON” where the user somehow generates the GATEON signal. This method would also require at least one additional pin. This also requires some interconnect that mimics the behaviour of the actual databus.